1. Field of the Invention
The invention relates to the generation of multiple related carrier frequencies using a phase locked loop, and in particular generates quadrature carriers at regularly spaced integer multiples of a given frequency.
2. Prior Art
A phase locked loop typically comprises a voltage controlled oscillator (VCO) operating at a relatively higher frequency that is a multiple of a desired lower output frequency. One or more frequency dividers in a feedback signal path counts down the oscillator frequency, providing one or more lower frequency outputs. A phase comparator compares one of the available frequencies to a reference signal. The output of the phase comparator is integrated and used to adjust the frequency of the voltage controlled oscillator up or down, causing the oscillator to track changes in the frequency of the reference signal over time.
In a configuration requiring a binary relationship between the oscillator frequency and desired lower frequency outputs, the frequency divider can comprise one or more serially cascaded divide-by-two stages (i.e., flip-flops). Each stage further divides the original VCO output signal frequency by two. In configurations that require frequencies that are related by other multiples (whether in the phase locked loop signal path or external to the path), counters and/or gate circuits can produce an output that divides the high frequency signal by providing an output on some recurring basis. Two or more parallel counters and/or gate arrangements that provide true outputs at some interval are possible for use in such circuits.
The outputs of such counters and gates can provide reference inputs to multiple phase comparators that control the frequencies of separate independently controlled VCOs. Typically, one VCO is used for each required output frequency that is not a multiple of another VCO frequency. Providing multiple VCOs is complex and can be expensive. There are performance issues with power consumption. The independent VCOs are independently controlled for tracking purposes, and are prone to crosstalk. It would be advantageous to provide a different, simpler and less expensive solution.
The elements of a phase locked loop, such as the VCO and frequency dividers, can be single phase devices or can be embodied as quadrature devices, i.e., wherein two synchronous signal phases are provided at a phase difference of 90 degrees (π/2 radians). Inasmuch as the quadrature signals are synchronous, it may be sufficient to provide a single phase control signal path in a phase locked loop, or only one phase may actually be needed to compare the signal against a reference input frequency at the phase comparator to control a VCO. Nevertheless, quadrature circuits are known for the oscillators and other elements of a phase locked loop, and are efficiently and inexpensively embodied in complementary circuit elements (e.g., CMOS).
An advantageous application for a quadrature phase locked loop is the generation of multiple carrier frequencies, each for quadrature amplitude modulation in a multiplexed communication system. In this disclosure, the terms “carrier” and “subcarrier” are used interchangeably. It would be beneficial if such a system could operate by multiplexing a relatively large number of relatively closely-spaced modulated subcarriers. The subcarriers can be sequentially adjacent integer multiples of the same frequency (a lowest frequency), wherein the highest integer multiple in the sequence is a frequency that defines the spacing between the center frequencies in the sequence of frequencies. This results in a bandwidth-efficient modulation technique.
A multiplex communication system using 16 microwave carriers, each of which carries a 16 point quadrature amplitude modulation signal, is described, for example, in “A 40 Gb/s SMC Optical Communication System based on an Integrated CMOS Transceiver,” ECOC-IOOC 2003 Proceedings, Vol. 4, pages 918-919, which is hereby incorporated in this disclosure. In the embodiment described in that article, a data bit rate was 666 Mb/s, per carrier, which bit rate can be supported by a digital signal processor that pipelines processing of incoming data bits. The carriers that are preferred are successive integer multiples of a frequency that defines the carrier spacing, in this case chosen as 833 MHz to provide inter-carrier separation as needed to minimize crosstalk and obtain a reasonably low error rate. One can calculate out that a resulting data capacity of 40 Gb/s is supported in a bandwidth span of 14 GHz, through a digital signal processor operating at 666 MHz.
What is still needed is an optimal way to generate the multiple closely spaced frequencies, such as sixteen separate quadrature phase carriers that are multiples of a predetermined basic frequency (e.g., one to sixteen times 833 MHz, respectively), in a manner that is robust and dependable, inexpensive, yet characterized by a precision and accuracy that enables the carrier frequencies to be modulated, transmitted, received, demodulated and decoded without undue noise.